1. Field of the Invention
The present invention relates to an information processing apparatus, an information processing method, and a storage medium.
2. Description of the Related Art
In recent years, a user of a device such as a smartphone and a tablet type personal computer has been able to freely download applications as the user desires. Thus, each user can customize the device by a method of performing software (SW) processing on the downloaded application with an arithmetic processing device such as a central processing unit (CPU). A configuration, in which customizing can be achieved by hardware (HW) processing in addition to the customizing by the SW processing, is expected to be an effective solution. More specifically, in the configuration, as the effective solution, the HW processing is freely executed on an additional function required by the user, with a device such as a field-programmable gate array (FPGA), which is one of techniques for dynamically changing hardware functions. This is because the processing speed of specific HW processing is much faster than that of the CPU processing, despite the increased speed of the CPU processing due to the advancement of semiconductors. The high speed HW processing may be essential for an apparatus such as a multifunction peripheral (MFP) that is required to execute real time processing on an input image.
A method of dynamically changing the hardware functions in a single piece of hardware configured of, for example, an FPGA, will be described below. In one method, all the hardware configuration data to be processed is stored in a storage device, such as a random access memory (RAM) connected to the FPGA, and is applied to the FPGA to be processed as appropriate. A technique of reducing time for rewriting the configuration data when the function is switched has been discussed, for example, in Japanese Patent Application Laid-Open No. 2000-89963. More specifically, all the pieces of configuration data are stored in the RAM, which can be accessed at a high speed, and only the configuration data required for the data processing is rewritten.
However, an amount of data storable on the RAM is limited. Thus, in the technique discussed in Japanese Patent Application Laid-Open No. 2000-89963, not all the pieces of configuration data can be loaded on the RAM when there are too many functions to be processed by the HW processing. As a result, when the configuration data that is not loaded on the RAM is used, the configuration data is read out from an external storage apparatus whose access speed is low, and to be applied to the FPGA. As a result, even though the HW processing is executed, a long processing time is required to obtain a result. The user may not have an advantage of the high processing speed by the HW processing in a case where a plurality of additional functions are to be added as customization. As the HW processing becomes more popular for customization in various fields such as smartphones, for executing the functions freely added by the user, the processing of a certain function, among the additional functions, however, may become much slower.
In a situation when too many functions are added, the HW processing or the SW processing may be selectively allocated to each function to be added. However, the functions are added not simultaneously but sequentially. Thus, the optimum sharing configuration of the HW processing and the SW processing may change each time a function is added. More specifically, in a case where a function, which takes a long processing time and thus is supposed to be processed by the HW processing, may be processed by the SW processing, when other additional functions have already occupied the capacity of a random access memory onto which the configuration data is to be loaded, a long processing time may be required.